This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-115209, filed Apr. 17, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a structure of a trench isolation region in a semiconductor device having a plurality of vertical MISFET cells, and is used for, for example, a power MISFET.
2. Description of the Related Art
In a conventional planar type power MISFET, the current path region and the breakdown voltage holding region are the same region, and there is a trade-off relationship that the ON-resistance increases if the region thickness is increased in order to increase the breakdown voltage, and on the other hand, the breakdown voltage decreases if the region thickness is decreased in order to decrease the ON-resistance, and it has been difficult to satisfy the both.
In contrast with the planar type power MISFET, a power MISFET having a super junction structure has been proposed.
FIG. 28 schematically shows a portion of a cross-sectional structure of an element portion of a 600 V system power MISFET having a conventional super junction structure.
When the super junction structured power MISFET is manufactured, an epitaxial growth Si layer of 5 to 8 xcexcm is formed on an Si substrate. Thereafter, a patterning and a boron (B) implantation are carried out to the epitaxially grown Si layer to form a p+-type region, and then, a patterning and a phosphorus (P) implantation are carried out to the epitaxially grown Si layer to form an n+-type region. Such a basic process is carried out about 6 times until the element is completed.
In other words, in such a manufacturing method, epitaxial growth is carried out as many as 6 times, and to form the p+type region and the n+-type region, patterning is carried out as many as 12 times and implantation is carried out as many as 12 times until the element is completed. Thus, the manufacturing steps greatly increases, and the manufacturing cost increases. A chip price of the element (Junction structure power MISFET) manufactured in this way becomes near to that of a large area chip of the planar type power MISFET (low ON-resistance type).
Moreover, it is difficult to make the dimension in the lateral direction (the dimension in the channel length direction) of the unit cell of the element to be fine. In fact, in a 600 V system power MISFET, the unit cell width of the element is about 30 xcexcm.
In consideration of such circumstances, in xe2x80x9cSemiconductor device and method of manufacturing the samexe2x80x9d of Japanese Patent KOKAI Publication No. 2002-170955 (Application No. 2001-285472), applicants of the present application have disclosed a three-layered pillar (for example, an NPN layer) structure which provides a function substantially the same as that of the super junction structure, and proposed a power MISFET which can cope with both low ON-resistance and high breakdown voltage and a manufacturing method which can manufacture the device without causing a great increase in the number of steps and thus decreases costs.
In the above-described proposal, a trench is formed in the epitaxial semiconductor layer on a semiconductor substrate in order to form the three-layered pillar. Then, a first conductivity type impurity and a second conductivity type impurity whose diffusion coefficient is smaller than the first conductivity type impurity are implanted into the side surface of the trench by an ion-implantation method, to change the epitaxial layer region between the adjacent trenches to the three-layered pillar structure due to the difference in diffusion coefficient.
In accordance with the above-described proposal, the three-layered pillar can be formed by implanting the first conductivity type impurity and the second conductivity type impurity, respectively, in the epitaxial layer only one time. The pn-junction between the p-type layer and the n-type layer in the three-layered pillar are formed so as to be substantially perpendicular to the main surface of the semiconductor substrate.
In the above-described proposal, as trench isolation films between the MISFET cells, an example was shown in which insulating films (an oxide film and a nitride film) cover a polycrystalline silicon layer formed on the semiconductor substrate and the bottom surface and the side surface of the trench provided in the polycrystalline silicon layer, or a polycrystalline silicon layer formed on the semiconductor substrate and the bottom surface, the side surface, and the upper surface of the trench provided in the polycrystalline silicon layer.
Further, a structure in which only an oxide film is filled in the trench between the MISFET cells is disclosed in xe2x80x9cVertical trench MISFET and method of manufacturing the samexe2x80x9d of U.S. Pat. No. 5,981,996. However, the details thereof are not disclosed.
According to a first aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate of a first conductivity type, which is a common drain of a plurality of MISFET cells; a plurality of semiconductor pillar regions each having first and second semiconductor pillar portions formed on a surface of the semiconductor substrate, the first and second semiconductor pillar portions having a vertically strip-shaped cross-section, the first semiconductor pillar portions having the first conductivity type, the second semiconductor pillar portion having a second conductivity type, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions; a base layer of the second conductivity type, which is formed in a surface of the second semiconductor pillar portion of each of the semiconductor pillar regions, the base layer having an impurity concentration which is higher than the second semiconductor pillar portions; a source diffusion layer of the first conductivity type, which is selectively formed in a surface of the base layer; a gate insulating film formed on a portion of the base layer, which is sandwiched by the source diffusion layer and each of the first semiconductor pillar portions; a gate electrode formed on the gate insulating film; and a plurality of isolation regions which isolates the semiconductor pillar regions from each other, the isolation regions being formed in trenches between the semiconductor pillar regions, the trenches being formed on the surface of the semiconductor substrate and reaching the surface of the semiconductor substrate, wherein each of the isolation regions comprises an oxide film formed on an inner surface of the trench and a nitride film formed on the oxide film, the nitride film being filled in the trench, and a film thickness ratio of the oxide film and the nitride film is in a range of 2:1 to 5:1.
According to a second aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate of a first conductivity type, which is a common drain of a plurality of MISFET cells; a plurality of semiconductor pillar regions each having first and second semiconductor pillar portions formed on a surface of the semiconductor substrate, the first and second semiconductor pillar portions having a vertically strip-shaped cross-section, the first semiconductor pillar portions having the first conductivity type, the second semiconductor pillar portion having a second conductivity type, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions; a base layer of the second conductivity type, which is formed in a surface of the second semiconductor pillar portion of each of the semiconductor pillar regions, the base layer having an impurity concentration which is higher than the second semiconductor pillar portion; a source diffusion layer of the first conductivity type, which is selectively formed in a surface of the base layer; a gate insulating film formed on a portion of the base layer, which is sandwiched by the source diffusion layer and each of the first semiconductor pillar portions; a gate electrode formed on the gate insulating film; and a plurality of isolation regions which isolates the semiconductor pillar regions from each other, the isolation regions being formed in trenches between the semiconductor pillar regions, the trenches being formed on the surface of the semiconductor substrate and reaching the surface of the semiconductor substrate, wherein each of the isolation regions comprises a first oxide film formed on an inner surface of the trench, a nitride film formed on the first oxide film, and a second oxide film formed to cover an upper surface of a cavity provided in the trench by the nitride film.
According to a third aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate of a first conductivity type, which is a common drain of a plurality of MISFET cells; a plurality of semiconductor pillar regions each having first and second semiconductor pillar portions formed on a surface of the semiconductor substrate, the first and second semiconductor pillar portions having a vertically strip-shaped cross-section, the first semiconductor pillar portions having the first conductivity type, the second semiconductor pillar portion having a second conductivity type, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portion; a base layer of the second conductivity type, which is formed in a surface of the second semiconductor pillar portion of each of the semiconductor pillar regions, the base layer having an impurity concentration which is higher than the second semiconductor pillar portions; a source diffusion layer of the first conductivity type, which is selectively formed in a surface of the base layer; a gate insulating film formed on a portion of the base layer, which is sandwiched by the source diffusion layer and each of the first semiconductor pillar portions; a gate electrode formed on the gate insulating film; and a plurality of isolation regions which isolates the semiconductor pillar regions from each other, the isolation regions being formed in trenches between the semiconductor pillar regions, the trenches being formed on the surface of the semiconductor substrate and reaching the surface of the semiconductor substrate, wherein each of the isolation regions comprises a first oxide film formed on an inner surface of the trench, a nitride film formed on the first oxide film, and a second oxide film formed on the nitride film, the second oxide film being doped with boron and phosphorus and filled in the trench.
According to a fourth aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate of a first conductivity type, which is a common drain of a plurality of MISFET cells; a plurality of semiconductor pillar regions each having first and second semiconductor pillar portions formed on a surface of the semiconductor substrate, the first and second semiconductor pillar portions having a vertically strip-shaped cross-section, the first semiconductor pillar portions having the first conductivity type, the second semiconductor pillar portion having a second conductivity type, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions; a base layer of the second conductivity type, which is formed in a surface of the second semiconductor pillar portion of each of the semiconductor pillar regions, the base layer having an impurity concentration which is higher than the second semiconductor pillar portion; a source diffusion layer of the first conductivity type, which is selectively formed in a surface of the base layer; a gate insulating film formed on a portion of the base layer, which is sandwiched by the source diffusion layer and each of the first semiconductor pillar portions; a gate electrode formed on the gate insulating film; and a plurality of isolation regions which isolates the semiconductor pillar regions from each other, the isolation regions being formed in trenches between the semiconductor pillar regions, the trenches being formed on the surface of the semiconductor substrate and reaching the surface of the semiconductor substrate, wherein each of the isolation regions comprises a first oxide film formed on an inner surface of the trench, a nitride film formed on the first oxide film, a second oxide film formed on the nitride film and doped with boron and phosphorus, a third oxide film formed to cover an upper surface of a cavity provided in the trench by the second oxide film.
According to a fifth aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate of a first conductivity type, which is a common drain of a plurality of MISFET cells; a plurality of semiconductor pillar regions each having first and second semiconductor pillar portions formed on a surface of the semiconductor substrate, the first and second semiconductor pillar portions having a vertically strip-shaped cross-section, the first semiconductor pillar portions having the first conductivity type, the second semiconductor pillar portion having a second conductivity type, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions; a base layer of the second conductivity type, which is formed in a surface of the second semiconductor pillar portion of each of the semiconductor pillar regions, the base layer having an impurity concentration which is higher than the second semiconductor pillar portion; a source diffusion layer of the first conductivity type, which is selectively formed in a surface of the base layer; a gate insulating film formed on a portion of the base layer, which is sandwiched by the source diffusion layer and each of the first semiconductor pillar portions; a gate electrode formed on the gate insulating film; and a plurality of isolation regions which isolates the semiconductor pillar regions from each other, the isolation regions being formed in trenches between the semiconductor pillar regions, the trenches being formed on the surface of the semiconductor substrate and reaching the surface of the semiconductor substrate, wherein each of the isolation regions comprises a silicon film formed in the trench.
According to a sixth aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate of a first conductivity type, which is a common drain of a plurality of MISFET cells; a plurality of semiconductor pillar regions each having first and second semiconductor pillar portions formed on a surface of the semiconductor substrate, the first and second semiconductor pillar portions having a vertically strip-shaped cross-section, the first semiconductor pillar portions having the first conductivity type, the second semiconductor pillar portion having a second conductivity type, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions; a base layer of the second conductivity type, which is formed in a surface of the second semiconductor pillar portion of each of the semiconductor pillar regions, the base layer having an impurity concentration which is higher than the second semiconductor pillar portion; a source diffusion layer of the first conductivity type, which is selectively formed in a surface of the base layer; a gate insulating film formed on a portion of the base layer, which is sandwiched by the source diffusion layer and each of the first semiconductor pillar portions; a gate electrode formed on the gate insulating film; and a plurality of isolation regions which isolates the semiconductor pillar regions from each other, the isolation regions being formed in trenches between the semiconductor pillar regions, the trenches being formed on the surface of the semiconductor substrate and reaching the surface of the semiconductor substrate, wherein each of the isolation regions comprises a porous silica film filled in the trench.
According to a seventh aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate of a first conductivity type, which is a common drain of a plurality of MISFET cells; a plurality of semiconductor pillar regions each having first and second semiconductor pillar portions formed on a surface of the semiconductor substrate, the first and second semiconductor pillar portions having a vertically strip-shaped cross-section, the first semiconductor pillar portion having the first conductivity type, the second semiconductor pillar portion having a second conductivity type, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions; a base layer of the second conductivity type, which is formed in a surface of the second semiconductor pillar portion of each of the semiconductor pillar regions, the base layer having an impurity concentration which is higher than the second semiconductor pillar portions; a source diffusion layer of the first conductivity type, which is selectively formed in a surface of the base layer; a gate insulating film formed on a portion of the base layer, which is sandwiched by the source diffusion layer and the first semiconductor pillar portion; a gate electrode formed on the gate insulating film; and
a plurality of isolation regions which isolates the semiconductor pillar regions from each other, the isolation regions being formed in trenches provided between the semiconductor pillar regions, the trenches being formed on the surface of the semiconductor substrate and reaching the surface of the semiconductor substrate, wherein each of the isolation regions comprises an particle composition oxide film made of oxide particles filled in the trench.